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Master theses

Current and past ideas and concepts for Master Theses.

FPGA's optimized design-space exploration


Xilinx’s Vivado HLS is a high-level synthesis tool based on Eclipse environment which generates HDL code for Xilinx’s FPGAs from C/C++ code. One of the main advantages of this tool is the fast Design Space Exploration (DSE) thanks to its compiler directives. Thus, several designs can be generated and tested in a short time. However, the large set of available directives does not facilitate the design user decisions. The main goal of this research is to adapt current optimization algorithms to HLS design exploration. These techniques must consider the main features of the FPGAs in order to achieve the optimal solution in the shortest time. The student will continue working on the current framework that already exists, composed by TCL scripts and Matlab code mainly.

Kind of work

• Analyze and compare different strategies in order to achieve a good performance design.

• Automate all the tasks which are user independent.

• Implement a plug-in for the Eclipse/Vivado HLS environment in order to explore a design space region and to test the most promising solutions on the board.

Framework of the Thesis

This thesis is related to the research track at the RapptorLab (INDI department) in collaboration with ETRO.

[1] Lemeire, Jan, et al. "Efficiency analysis methodology of FPGAs based on lost frequencies, area and cycles." Journal of Parallel and Distributed Computing 113 (2018): 204-217.

[2] da Silva, Bruno, et al. "A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis." International Symposium on Applied Reconfigurable Computing. Springer, Cham, 2016.

Number of Students


Expected Student Profile

• Basic knowledge of/ experience in FPGAs.
• Interest in Machine Learning.
• Matlab/C/C++/Java programming experience and/or interest.


Mr. Abdellah Touhafi

+32 (0)2 629 3774

more info


Mr. Bruno da Silva Gomes

+32 (0)2 629 3768

more info

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