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PhD Defense


Mr Jorge Lagos Benites - ETRO, VUB and IMEC [Email]


The ever-increasing demand for higher data throughput has fueled the development of
analog-to-digital converters (ADCs) that seek to maximize both linearity and bandwidth.
Typical applications that benefit from such ADCs include software-defined radios, cellular
base stations, satellite and radar receivers, cable TV set-top units, and instrumentation
equipment, in which the adoption of wide-bandwidth, high-speed ADCs provides
benefits in terms of system complexity reduction and reconfigurability.
The predominant architecture for the implementation of such high-performance ADCs
is the time-interleaved pipeline, in which the power efficiency is limited by the operational
amplifiers used for residue generation, which are characterized by their high power
consumption and poor scaling properties. Moreover, since their gain-bandwidth is often
insufficient, the problem of nonlinear incomplete settling must be addressed in the digital
domain through high-order gain calibration.
This work presents an approach for the realization of high performance ADCs in lowvoltage
nanoscale CMOS processes, based on ring amplification. The approach leverages
the favorable speed and output-swing properties of the ring amplifier together with 1storder
gain calibration to simultaneously achieve high bandwidth and linearity, and its
effectiveness is demonstrated by means of two 12-bit single-channel pipelined ADC implementations
in a 0.9-V, 28-nm CMOS process.
The first implementation introduces a speed-optimized ring amplifier in which a tunable
dead-zone is generated by means of an anti-parallel arrangement of CMOS devices,
and an active common-mode feedback circuit that uses a variant of the proposed ringamp
to satisfy the need for robust, fast and power-efficient common-mode regulation.
In the second implementation, two techniques are introduced to further extend the
limits of the proposed ring amplifier: dead-zone degeneration, to improve output-swing
and thus linearity, and 2nd-stage bias enhancement, to improve settling and thus speed.
The performance demonstrated by these implementations renders them not only the
highest-speed ring-amplifier-based ADCs reported to date, but also the most power efficient
implementations among all single-channel ADCs of any architecture with at least
600 MS/s and greater than 9 ENOB.

Short CV

MSc. in Nanotechnologies for ICTs, Politecnico di Torino/INP Grenoble/Ecole Polytechnique de Lausanne, 2013


Date: 02.05.2019

Time: 16:00

Location: Room D.2.01 Building D

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