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PhD Defense
HIGH-SPEED CMOS CIRCUITS FOR MM-WAVE COMMUNICATION AND SENSING

Presenter

Mr. Oscar Elio Mattia - ETRO, VUB and IMEC [Email]

Abstract

The large bandwidth available at mm-wave frequencies presents an opportunity to dramatically improve wireless communications and remote sensing. In wireless communication, the large available unlicensed spectrum around 60 GHz allows more than 30 Gbps of raw data-rate for a single transceiver. The capability of downscaled CMOS to operate at mm-wave frequencies enables compact radar systems with a resolution in the centimeter range. These two applications require multi-GHz baseband processing in a power efficient and compact manner. Modern CMOS IC technology is an excellent candidate for that task and this is the focus of this work.
The first half of the thesis deals with a non-oversampling mixed-signal receiver baseband for wireless communication, that can operate with symbol rates up to 9 Gsamples per second. Instead of using a traditional oversampling analog-to-digital converter (ADC) and digital signal processing, which are both power hungry at these symbol rates, the operations of carrier synchronization, channel equalization, digitization and demodulation of the data are performed in a mixed-signal environment, resulting in significant power savings. A system-level study, including front-end non-idealities and the propagation channel characteristics, shows the feasibility of such an architecture. An implementation in 28 nm CMOS of the main building block, a 36 Gbps 16-QAM 5-tap decision feedback equalizer, is described.
The second part of the thesis investigates the requirements for a phase-modulated continuous-wave (PMCW) radar receiver baseband section. The main properties of the binary modulation sequence are covered from a radar perspective and the effect of non-idealities in the signal path is analyzed with emphasis on signal harmonic distortion and ADC time-interleaving (TI) artifacts. A second hardware implementation in 28 nm CMOS is presented, consisting of a 2 GS/s 9-bit 8-12x time-interleaved pipelined-successive approximation register (SAR) ADC, which is part of a bigger PMCW radar system on chip.

Short CV

Master of Science in Microelectronics, Universidade Federal do Rio Grande do Sul, 2014

Logistics

Date: 23.08.2019

Time: 15:00

Location: Room D.2.01 Building D

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