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Journal Publication

A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS

This publication appears in: IEEE JOURNAL OF SOLID-STATE CIRCUITS

Authors: J. Luis Lagos Benites, B. Hershberg, E. Martens, P. Wambacq and J. Craninckx

Volume: 54

Issue: 2

Pages: 403-416

Publication Date: Nov. 2018


Abstract:

Achieving high linearity and bandwidth with good power efficiency makes the design of ADCs in deep nanoscale CMOS processes very challenging, as the constraints of low-voltage operation and limited intrinsic gain often dictate the use of power-consuming analog circuits and intensive digital calibration. This paper addresses these problems by introducing a pipelined ADC that exploits the low but very constant open-loop gain versus output voltage characteristic of the ring amplifier (ringamp) to achieve both high speed and linearity in low-voltage nanoscale CMOS designs. A tunable ringamp biasing scheme using an anti-parallel arrangement of CMOS transistors and an active ringamp-based common-mode feedback are also introduced. A single-channel prototype ADC is implemented in a standard 28-nm CMOS process, achieving 58.7-dB SNDR and 72.4-dB SFDR at 600 MS/s while consuming 14.5 mW from a single 0.9-V supply, resulting in Walden and Schreier figure-of-merit (FoM) values of 34.4 fJ/conv.-step and 161.9 dB, respectively.

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Mr. Jorge Luis Lagos Benites

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jlagosbe@etrovub.be

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Prof. Piet Wambacq

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pwambacq@etrovub.be

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