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Conference Publication

A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/Ás Slope and 1.2GHz Chirp Bandwidth

Host Publication: 2020 International Solid-State Circuits Conference

Authors: P. Renukaswamy, N. Markulic, S. Park, A. Kankuppe Raghavendra Swamy, Q. Shi, P. Wambacq and J. Craninckx

UsePubPlace: San Francisco

Publisher: Institute of Electrical and Electronics Engineers ( IEEE )

Publication Date: Feb. 2020

Number of Pages: 3


Abstract:

A 10GHz FMCW subsampling PLL is presented, that uses a low-power charge-integrating QDAC to tune the VCO for wideband low-noise modulation. Nonlinearities in the QDAC modulation path are corrected within 700µsec cold start-up, followed by a full on-chip background calibration engine to track supply and temperature variations. The PLL consumes 11.7mW (of which <0.5mW in the QDAC) to generate a 23.6MHz/µs chirp slope with 89kHz rms-frequency-error for 1.21GHz chirp-bandwidth.

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Current ETRO Authors

Mr. Pratap Renukaswamy

+32 (0)02 629 152

ptrenuka@etrovub.be

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Mr. Sehoon Park

+32 (0)02 629 152

spark@etrovub.be

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Mr. Anirudh Kankuppe Raghavendra Swamy

+32 (0)02 629 152

apraveen@etrovub.be

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Prof. Piet Wambacq

+32 (0)16 281 218

pwambacq@etrovub.be

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