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A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/Ás Slope and 1.2-GHz Chirp-Bandwidth

This publication appears in: IEEE Journal of Solid - State Circuits

Authors: P. Renukaswamy, N. Markulic, P. Wambacq and J. Craninckx

Volume: 2020

Number of Pages: 14

Publication Date: Sep. 2020


Abstract:

A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/µs sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.

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Mr. Pratap Renukaswamy

+32 (0)02 629 152

ptrenuka@etrovub.be

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Prof. Piet Wambacq

+32 (0)16 281 218

pwambacq@etrovub.be

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