A Single-Channel, 600Msps, 12bit, Ringamp-Based Pipelined ADC in 28nm CMOS
Host Publication: 2017 Symposium on VLSI Circuits
Authors: J. Luis Lagos Benites, B. Hershberg, E. Martens, P. Wambacq and J. Craninckx
Publisher: Institute of Electrical and Electronics Engineers ( IEEE )
Publication Date: Jun. 2017
Number of Pages: 2
A pipelined ADC is presented that exploits the low but very constant (over output swing) open-loop gain characteristic of the ring amplifier to achieve high SFDR in low-voltage nanoscale CMOS designs. A dynamic ringamp biasing scheme using CMOS resistors and an active ringamp-based common-mode feedback are also introduced. The implemented prototype achieves 56.3dB SNDR and 69.2dB SFDR at 600Msps, consuming 14.2mW from a 0.9V supply, resulting in a Figure-of-Merit of 44.3fJ/conv.-step.