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Conference Publication

A fully-integrated method for RTN parameter extraction

Host Publication: Symposium on VLSI Technology

Authors: M. Simicic, S. Morrison, B. Parvais, P. Weckx, B. Kaczer, K. Sawada, H. Ammo, S. Yamakawa, K. Nomoto, M. Ohno, D. Linten, D. Verkest, P. Wambacq, G. Groeseneken and G. Gielen

Publisher: Institute of Electrical and Electronics Engineers Inc

Publication Date: Jul. 2017

ISBN: 9784863486058


Abstract:

© 2017 JSAP. A method for on-chip extraction of random telegraph noise (RTN) parameters from transistors is proposed. Exploiting the nature of exponential distributed RTN events, the proposed circuit enables the automatic extraction of mean RTN time constants from a large array of small-area transistors. The on-chip data processing provides a simplified measurement infrastructure, reduces the measurement time by parallelization and increased efficiency, reduces the data post-processing effort and extends the measurement frequency band. The methodology is demonstrated in a prototype chip fabricated in a 28nm High-k Metal Gate (HK/MG) CMOS technology. The 1.17 mm 2 chip includes two arrays of 18,144 transistors each, analog circuitry for sensing and digitizing the RTN signals and a digital signal processing block. The experimental results agree with expectations.

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