Defect-based compact modeling for RTN and BTI variability
Host Publication: International reliability symposium
Authors: P. Weckx, M. Simicic, K. Nomoto, M. Ono, B. Parvais, B. Kaczer, P. Raghavan, D. Linten, K. Sawada, H. Ammo, S. Yamakawa, A. Spessot, D. Verkest and A. Mocuta
Publisher: Institute of Electrical and Electronics Engineers Inc
Publication Date: May. 2017
© 2017 IEEE. This paper describes a defect-centric based compact modeling methodology for time-dependent threshold voltage variability (V TH ), induced by Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN). A Verilog-A based model wrapper is used to implement a threshold voltage shift by adding a variable voltage source at the gate of the core device model. This compact model allows to incorporate all BTI and RTN related electrostatics and kinetics in standard EDA-Tools as a 'black box' without any custom simulation flow. It can therefore be used in either a manual configuration for academic purposes or be integrated as is into industry standard EDA tools and simulation flows.