A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability
This publication appears in: Microelectronics Reliability
Authors: B. Kaczer, J. Franco, P. Weckx, P. Roussel, V. Putcha, E. Bury, M. Simicic, A. Chasin, D. Linten, B. Parvais, F. Catthoor, G. Rzepa, M. Waltl and T. Grasser
Publication Date: Feb. 2018
A paradigm for MOSFET instabilities is outlined based on gate oxide traps and the detailed understanding of their properties. A model with trap energy levels in the gate dielectric and their misalignment with the channel Fermi level is described, offering the most successful strategy to reduce both Positive and Negative Bias Temperature Instability (PBTI and NBTI) in a range of gate stacks. Trap temporal properties are determined by tunneling between the carrier reservoir and the trap itself, as well as thermal barriers related to atomic reconfiguration. Trap electrostatic impact depends on the gate voltage and its spatial position, randomized by variations in the channel potential. All internal properties of traps are distributed, resulting in distributions of the externally observable trap parameters, and in turn in time-dependent variability in devices and circuits.