Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
Host Publication: 63rd IEEE International Electron Devices Meeting, IEDM 2017
Authors: D. Yakimets, M. Garcia Bardon, D. Jang, P. Schuddinck, Y. Sherazi, P. Weckx, K. Miyaguchi, B. Parvais, P. Raghavan, A. Spessot, D. Verkest and A. Mocuta
Publisher: Institute of Electrical and Electronics Engineers Inc
Publication Date: Jan. 2018
In this paper, we show how 5.5 tracks standard cells can be enabled at gate pitch 42 nm and metal pitch 21 nm and achieve 60% active power reduction from the 7nm node. A device downselection methodology driven by power and performance targets is introduced. This method demonstrates that three stacked nanosheets of 20 nm width are competitive with FinFETs made with two fins while relaxing the constraints on layout design rules.