3D technologies for analog/RF applications
Host Publication: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Authors: A. Vandooren, B. Parvais, A. Walke, A. Vais, C. Merckling, D. Lin, N. Waldron, P. Wambacq, D. Mocuta and N. Collaert
Publisher: Institute of Electrical and Electronics Engineers Inc
Publication Date: Mar. 2018
Number of Pages: 3
In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.