Publication Details
Y. Xiang, M. Garcia Bardon, B. Kaczer, Md Nur K. Alam, L.-A. Ragnarsson, K. Kaczmarek, Bertrand Parvais, G. Groeseneken, J. Van Houdt

IEEE Transactions on Electron Devices

Contribution To Journal


The (doped-)hafnia-based' ferroelectric FET (FeFET) is a promising candidate for low-power nonvolatile memories and shows potential use as a steep-slope low-power logic device. This requires accurate modeling of the metal-ferroelectric-insulator-silicon (MFIS) gate stack electrostatics. Here, we present a hardware-validated FeFET compact model that resolves three key aspects in the MFIS electrostatics pertaining to a multidomain ferroelectric (FE) layer: 1) the nonradiative multiphonon process-based charge trapping 2) the source-to-drain channel percolation due to spatial nonuniformity of FE domain switching and 3) the nucleation-growth domain reversal dynamics using a phenomenological formalism. The polarization charge is calculated by discretized domain switching in transient under distributed coercive fields. Based on the comparison of the model versus experimental data on Hf0.5Zr0.5O2 n-FeFET hardware, we prove that the onset of FE VTH lowering starts with the source-to-drain percolation path formation when enough FE domains have been flipped up by the gate bias. We further demonstrate that the field-independent domain growth is the fundamental origin of the measured steep subthreshold slope during the downward ID-VG sweep. The model ultimately aims to lay down the groundwork for a unified FeFET compact model for both memory- and logic-oriented applications.

DOI scopus