Verbruggen, B., Craninckx, J., Kuijk, M., Wambacq, P., & Van Der Plas, G. (2010). A 2.6 mW 6b 2.2GS/S 4-times Interleaved Fully Dynamic Pipelined ADC in 40 nm Digital CMOS. In IEEE International Solid-State Circuits Conference (ISSCC) (pp. 296-297). (IEEE International Solid-State Circuits Conference (ISSCC)). IEEE.

@inproceedings{7dbfe24dc738472e85a6ac6e2891974e,
title = "A 2.6 mW 6b 2.2GS/S 4-times Interleaved Fully Dynamic Pipelined ADC in 40 nm Digital CMOS",
abstract = "A 2.2 GS/S 4*-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. Threshold calibration corrects for amplifier and comparator imperfections and 31.6 dB SNDR is achieved with 2 GHz ERBW for 2.6 mW power consumption",
keywords = "amplifiers, analogue-digital conversion, calibration, CMOS digital integrated circuits, comparators, low-power electronics",
author = "Bob Verbruggen and J. Craninckx and Maarten Kuijk and Piet Wambacq and {Van Der Plas}, G.",
year = "2010",
month = feb,
day = "7",
language = "English",
isbn = "978-1-4244-6033-5",
series = "IEEE International Solid-State Circuits Conference (ISSCC)",
publisher = "IEEE",
pages = "296--297",
booktitle = "IEEE International Solid-State Circuits Conference (ISSCC)",
note = "Unknown ; Conference date: 07-02-2010",
}