Collaert, N., Von Arnim, K., Rooyackers, R., Vandeweyer, T., Mercha, A., Parvais, B., Witters, L., Nackaerts, A., Sanchez, E. A., Demand, M., Hikavyy, A., Demuynck, S., Devriendt, K., Bauer, F., Ferain, I., Veloso, A., De Meyer, K., Biesemans, S., & Jurczak, M. (2010). Low-voltage scaled 6T FinFET SRAM cells. In Emerging Technologies and Circuits (pp. 55-66). (Lecture Notes in Electrical Engineering; Vol. 2021 LNEE). https://doi.org/10.1007/978-90-481-9379-0_4

@inproceedings{446ccd75e469417faf53b131b46f8960,
title = "Low-voltage scaled 6T FinFET SRAM cells",
abstract = "Planar bulk devices suffer from high random dopant fluctuations (RDF) when scaled down to sub-32 nm technology nodes. This is considered as a major roadblock for the integration of these devices in high density 6T SRAM cells [1, 2]. The increasing variation of transistor parameters like VT, ION, IOFF, etc., can result in a large variability in performance and power. The possibility of leaving the channels undoped and their excellent immunity against Short Channel Effects (SCE) favors the use of FinFET-based multi-gate devices [3] for these technology nodes.",
author = "N. Collaert and {Von Arnim}, K. and R. Rooyackers and T. Vandeweyer and A. Mercha and B. Parvais and L. Witters and A. Nackaerts and Sanchez, {E. Altamirano} and M. Demand and A. Hikavyy and S. Demuynck and K. Devriendt and F. Bauer and I. Ferain and A. Veloso and {De Meyer}, K. and S. Biesemans and M. Jurczak",
year = "2010",
month = nov,
day = "15",
doi = "10.1007/978-90-481-9379-0_4",
language = "English",
isbn = "9789048193783",
series = "Lecture Notes in Electrical Engineering",
pages = "55--66",
booktitle = "Emerging Technologies and Circuits",
note = "International Conference on Integrated Circuit Design and Technology, ICICDT 2008 ; Conference date: 02-06-2008 Through 04-06-2008",
}