Nowadays, sub-45 nm designs are facing the challenges of parametric yield loss and reliability issues. Existing design practices increase the system's area/power penalty in order to cope with the growing number of design corners and their widening distributions. Our proposed solution is the Standardized Knobs and Monitors (SKM) framework, which enables monitoring and adjusting the circuits at run-time by utilizing power-delay trade-offs. More specifically, we focus on the systematic insertion of digital monitors at the RTL level of design abstraction and demonstrate our approach by using modified crystal ball delay monitor in a real-life wireless application
Abd Elhamid Abd Elhamid, A, Anchlia, A, Mamagkakis, S, Miranda, MC, Dierickx, B & Kuijk, M 2009, A standardized knobs and monitors RTL2RTL insertion methodology for fine grain SoC tuning. in Proceedings of the 2009 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009). vol. 12, IEEE, pp. 401-408, 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009), Patras, Greece, 27/08/09.
Abd Elhamid Abd Elhamid, A., Anchlia, A., Mamagkakis, S., Miranda, M. C., Dierickx, B., & Kuijk, M. (2009). A standardized knobs and monitors RTL2RTL insertion methodology for fine grain SoC tuning. In Proceedings of the 2009 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009) (Vol. 12, pp. 401-408). IEEE.
@inproceedings{346ee5519b1a42e7aea1e35aa42845b5,
title = "A standardized knobs and monitors RTL2RTL insertion methodology for fine grain SoC tuning",
abstract = "Nowadays, sub-45 nm designs are facing the challenges of parametric yield loss and reliability issues. Existing design practices increase the system's area/power penalty in order to cope with the growing number of design corners and their widening distributions. Our proposed solution is the Standardized Knobs and Monitors (SKM) framework, which enables monitoring and adjusting the circuits at run-time by utilizing power-delay trade-offs. More specifically, we focus on the systematic insertion of digital monitors at the RTL level of design abstraction and demonstrate our approach by using modified crystal ball delay monitor in a real-life wireless application",
keywords = "circuit tuning, integrated circuit design, integrated circuit reliability, integrated circuit testing, nanoelectronics",
author = "{Abd Elhamid Abd Elhamid}, Ahmed and A Anchlia and S Mamagkakis and M.c. Miranda and Bart Dierickx and Maarten Kuijk",
year = "2009",
month = aug,
day = "27",
language = "English",
isbn = "978-0-7695-3782-5",
volume = "12",
pages = "401--408",
booktitle = "Proceedings of the 2009 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009)",
publisher = "IEEE",
note = "12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009) ; Conference date: 27-08-2009 Through 29-08-2009",
}