A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ∼5 {\AA} and ∼8 {\AA} respectively for both n and pMOS devices. The drive currents at Ioff=100 nA/μm with VDD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS VT of 0.3/-0.4V, good V T-uniformity, and VT-matching and very high cutoff frequencies at ∼290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.
Ragnarsson, LÃ…, Li, Z, Tseng, J, Schram, T, Rohr, E, Cho, MJ, Kauerauf, T, Conard, T, Okuno, Y, Parvais, B, Absil, P, Biesemans, S & Hoffmann, TY 2009, Ultra low-EOT (5 Ã…) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization. in 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest., 5424254, Technical Digest - International Electron Devices Meeting, IEDM, pp. 28.5.1-28.5.4, 2009 International Electron Devices Meeting, IEDM 2009, Baltimore, MD, United States, 7/12/09. https://doi.org/10.1109/IEDM.2009.5424254
Ragnarsson, L. Ã…., Li, Z., Tseng, J., Schram, T., Rohr, E., Cho, M. J., Kauerauf, T., Conard, T., Okuno, Y., Parvais, B., Absil, P., Biesemans, S., & Hoffmann, T. Y. (2009). Ultra low-EOT (5 Ã…) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization. In 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest (pp. 28.5.1-28.5.4). Article 5424254 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2009.5424254
@inproceedings{81137de2cfb44f58889bdb63938417ed,
title = "Ultra low-EOT (5 {\AA}) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization",
abstract = "A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ∼5 {\AA} and ∼8 {\AA} respectively for both n and pMOS devices. The drive currents at Ioff=100 nA/μm with VDD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS VT of 0.3/-0.4V, good V T-uniformity, and VT-matching and very high cutoff frequencies at ∼290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.",
author = "Ragnarsson, {L. {\AA}} and Z. Li and J. Tseng and T. Schram and E. Rohr and Cho, {M. J.} and T. Kauerauf and T. Conard and Y. Okuno and B. Parvais and P. Absil and S. Biesemans and Hoffmann, {T. Y.}",
year = "2009",
month = dec,
day = "1",
doi = "10.1109/IEDM.2009.5424254",
language = "English",
isbn = "9781424456406",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
pages = "28.5.1--28.5.4",
booktitle = "2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest",
note = "2009 International Electron Devices Meeting, IEDM 2009 ; Conference date: 07-12-2009 Through 09-12-2009",
}