A new scalable compact model for the resistive substrate network of multi-finger MOSFETs is presented. The model is based on the transmission line formalism to capture the distributed nature of the well resistance. Due to its physical foundation, the model provides a more accurate description of different layout styles over a wide range of geometries. The model is validated experimentally on a 90 nm CMOS technology and is used to determine the geometry of RF transistors that minimize the substrate resistance. The opted network topology allows a direct implementation with the PSP model.
Parvais, B, Hu, S, Dehan, M, Mercha, A & Decoutere, S 2007, An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs. in Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007., 4405781, Proceedings of the Custom Integrated Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 503-506, 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007, San Jose, United States, 16/09/07. https://doi.org/10.1109/CICC.2007.4405781
Parvais, B., Hu, S., Dehan, M., Mercha, A., & Decoutere, S. (2007). An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 503-506). Article 4405781 (Proceedings of the Custom Integrated Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405781
@inproceedings{8a9e83e689494bbeab32a4e5f4a3d856,
title = "An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs",
abstract = "A new scalable compact model for the resistive substrate network of multi-finger MOSFETs is presented. The model is based on the transmission line formalism to capture the distributed nature of the well resistance. Due to its physical foundation, the model provides a more accurate description of different layout styles over a wide range of geometries. The model is validated experimentally on a 90 nm CMOS technology and is used to determine the geometry of RF transistors that minimize the substrate resistance. The opted network topology allows a direct implementation with the PSP model.",
author = "B. Parvais and S. Hu and M. Dehan and A. Mercha and S. Decoutere",
year = "2007",
month = jan,
day = "1",
doi = "10.1109/CICC.2007.4405781",
language = "English",
isbn = "1424407869",
series = "Proceedings of the Custom Integrated Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "503--506",
booktitle = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007",
address = "United States",
note = "29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 ; Conference date: 16-09-2007 Through 19-09-2007",
}