Publication Details
Overview
 
 
Bertrand Parvais, M. Dehan, V. Subramanian, A. Mercha, K. Tamer San, M. Jurczak, G. Groeseneken, W. Sansen, S. Decoutere
 

Chapter in Book/ Report/ Conference proceeding

Abstract 

FinFET architecture results in high level of parasitics that offset the performance gain that can be achieved through gate length scaling. In this work, we investigate technological solutions both at the process integration and layout levels to alleviate these limitations. Layout guidelines are derived to improve the RF performance. For an optimized layout folding, experiments indicate 15% gain in fT.

Reference 
 
 
DOI  scopus