Maillard, X., Kuijk, M., & Devisch, F. (2002). A 900-Mbit/s CMOS Data Recovery DLL using Half-Frequency Clock. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 37, 711-715. http://www.etro.vub.ac.be/Members/maillard.xavier/jssc.pdf

@article{e7e6ba86f30940999cb2c87ff0eb4f80,
title = "A 900-Mbit/s CMOS Data Recovery DLL using Half-Frequency Clock",
abstract = "A data recovery delay-locked loop (DLL) for non-return-to-zero (NRZ) data transmission is described. A reference clock is delayed for triggering a latch that samples the incoming NRZ data stream. The data rate can be twice the reference clock frequency. The circuit has a proportional nondead-zone sampling phase detector that also serves the role of charge pump. A self-correcting function reduces the problem of the finite phase capture range associated with conventional DLLs. The prototype circuit is fabricated in 2.5-V 0.25-mum CMOS and occupies an area of only 270 x 50 mum(2). It is demonstrated that at 900-Mb/s NRZ data, jitter is reduced from 118.2- to 31.3-ps rms jitter for a power consumption of only 3 mW",
keywords = "PHASE-LOCKED LOOP, PLL, phase detector",
author = "Xavier Maillard and Maarten Kuijk and Frederic Devisch",
note = "journal of solid-state circuits, Vol. 27, pp. 711-715.",
year = "2002",
month = jun,
day = "1",
language = "English",
volume = "37",
pages = "711--715",
journal = "IEEE JOURNAL OF SOLID-STATE CIRCUITS",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
}