This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and low- area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.
Renukaswamy, P, Markulic, N, Wambacq, P & Craninckx, J 2021, Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. in Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation., 9401690, 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), Institute of Electrical and Electronics Engineers ( IEEE ), Daegu, Korea, pp. 1-5, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, Republic of, 22/05/21. https://doi.org/10.1109/ISCAS51556.2021.9401690
Renukaswamy, P., Markulic, N., Wambacq, P., & Craninckx, J. (2021). Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. In Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation (pp. 1-5). Article 9401690 (2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)). Institute of Electrical and Electronics Engineers ( IEEE ). https://doi.org/10.1109/ISCAS51556.2021.9401690
@inproceedings{6226417b0c0047c89b516d1f3b061227,
title = "Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation",
abstract = "This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and low- area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.",
author = "Pratap Renukaswamy and Nereo Markulic and Piet Wambacq and Jan Craninckx",
note = "Publisher Copyright: {\textcopyright} 2021 Institute of Electrical and Electronics Engineers Inc.. All rights reserved. Copyright: Copyright 2021 Elsevier B.V., All rights reserved.; 2021 IEEE International Symposium on Circuits and Systems (ISCAS) ; Conference date: 22-05-2021 Through 28-05-2021",
year = "2021",
month = may,
day = "22",
doi = "10.1109/ISCAS51556.2021.9401690",
language = "English",
isbn = "978-1-7281-9201-7",
series = "2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)",
publisher = "Institute of Electrical and Electronics Engineers ( IEEE )",
pages = "1--5",
booktitle = "Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation",
url = "https://iscas2021.org/",
}