Top tier devices in a 3D sequential integration are optimized using a low temperature process flow (< 525°C}). Bi-axial tensile strained silicon is transferred without strain relaxation to boost the top tier nmos device performance by 40-50% over the unstrained silicon devices, recovering the performance loss from the low temperature processing when using extension-less device integration. Excimer laser anneal is also shown to effectively activate both n-type and p-type dopants in the extension of thin silicon film devices using optimized, CMOS compatible, laser exposure conditions. Laser anneal is fully compatible with a replacement metal gate (RMG) process flow and with selective source/drain (SD) epitaxy. The dopant activation level is preserved during the entire process flow which results in similar Ion Ioff device performance for devices with laser and spike anneals. Excimer laser anneal benefits also from improved control short channel effects over spike annealing due to low dopant diffusion.
Vandooren, A, Wu, Z, Parihar, N, Franco, J, Parvais, B, Matagne, P, Debruyn, H, Mannaert, G, Devriendt, K, Teugels, L, Vecchio, E, Radisic, D, Rosseel, E, Hikavyy, A, Chan, BT, Waldron, N, Mitard, J, Besnard, G, Alvarez, A, Gaudin, G, Schwarzenbach, W, Radu, I, Nguyen, BY, Huet, K, Tabata, T, Mazzamuto, F, Demuynck, S, Boemmels, J, Collaert, N & Horiguchi, N 2020, 3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters. in 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings., 9265026, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2020-June, Institute of Electrical and Electronics Engineers Inc., pp. 1-2, 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020, Honolulu, United States, 16/06/20. https://doi.org/10.1109/VLSITechnology18217.2020.9265026
Vandooren, A., Wu, Z., Parihar, N., Franco, J., Parvais, B., Matagne, P., Debruyn, H., Mannaert, G., Devriendt, K., Teugels, L., Vecchio, E., Radisic, D., Rosseel, E., Hikavyy, A., Chan, B. T., Waldron, N., Mitard, J., Besnard, G., Alvarez, A., ... Horiguchi, N. (2020). 3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters. In 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings (pp. 1-2). Article 9265026 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2020-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnology18217.2020.9265026
@inproceedings{8cce571d911449ac8c496b3083f77d91,
title = "3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters",
abstract = "Top tier devices in a 3D sequential integration are optimized using a low temperature process flow (< 525°C}). Bi-axial tensile strained silicon is transferred without strain relaxation to boost the top tier nmos device performance by 40-50% over the unstrained silicon devices, recovering the performance loss from the low temperature processing when using extension-less device integration. Excimer laser anneal is also shown to effectively activate both n-type and p-type dopants in the extension of thin silicon film devices using optimized, CMOS compatible, laser exposure conditions. Laser anneal is fully compatible with a replacement metal gate (RMG) process flow and with selective source/drain (SD) epitaxy. The dopant activation level is preserved during the entire process flow which results in similar Ion Ioff device performance for devices with laser and spike anneals. Excimer laser anneal benefits also from improved control short channel effects over spike annealing due to low dopant diffusion. ",
author = "A. Vandooren and Z. Wu and N. Parihar and J. Franco and B. Parvais and P. Matagne and H. Debruyn and G. Mannaert and K. Devriendt and L. Teugels and E. Vecchio and D. Radisic and E. Rosseel and A. Hikavyy and Chan, {B. T.} and N. Waldron and J. Mitard and G. Besnard and A. Alvarez and G. Gaudin and W. Schwarzenbach and I. Radu and Nguyen, {B. Y.} and K. Huet and T. Tabata and F. Mazzamuto and S. Demuynck and J. Boemmels and N. Collaert and N. Horiguchi",
year = "2020",
month = jun,
doi = "10.1109/VLSITechnology18217.2020.9265026",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--2",
booktitle = "2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings",
address = "United States",
note = "2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 ; Conference date: 16-06-2020 Through 19-06-2020",
}