A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/µs sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.
Renukaswamy, P, Markulic, N, Wambacq, P & Craninckx, J 2020, 'A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth', IEEE Journal of Solid - State Circuits, vol. 55, no. 12, 9197684, pp. 3294-3307. https://doi.org/10.1109/JSSC.2020.3021311
Renukaswamy, P., Markulic, N., Wambacq, P., & Craninckx, J. (2020). A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. IEEE Journal of Solid - State Circuits, 55(12), 3294-3307. Article 9197684. https://doi.org/10.1109/JSSC.2020.3021311
@article{07870bb4a8994f7cbb658070e7a1cdfa,
title = "A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth",
abstract = "A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/µs sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.",
author = "Pratap Renukaswamy and Nereo Markulic and Piet Wambacq and Jan Craninckx",
note = "Funding Information: Manuscript received April 24, 2020; revised June 27, 2020 and August 20, 2020; accepted August 25, 2020. Date of publication September 15, 2020; date of current version November 24, 2020. This article was approved by Associate Editor Jaehyouk Choi. This work was supported by the European Community{\textquoteright}s ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE. (Corresponding author: Pratap Tumkur Renukaswamy.) Pratap Tumkur Renukaswamy and Piet Wambacq are with imec, 3001 Leu-ven, Belgium, and also with the Department ETRO, Vrije Universiteit Brussel, 1050 Brussels, Belgium (e-mail: pratap.renukaswamy@imec.be; piet.wambacq@imec.be). Funding Information: This work was supported by the European Community's ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE. Publisher Copyright: {\textcopyright} 1966-2012 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.",
year = "2020",
month = sep,
day = "15",
doi = "10.1109/JSSC.2020.3021311",
language = "English",
volume = "55",
pages = "3294--3307",
journal = "IEEE Journal of Solid - State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "12",
}