This article analyses and demonstrates a 22.5â27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of the automatic bandwidth control, on the effect of the gear-shift algorithm for fast lock and on the different noise contributions. The proposed gear-shift algorithm scales up the PLL bandwidth for faster acquisition and orderly reduces it for jitter performance. The PLL contains a digitally controlled oscillator (DCO) based on transformer feedback with a tunable source-bridged capacitor, which allows for a low phase noise (PN) over a wide tuning range (FoM of â184 dBc/Hz and FoM T of â191 dBc/Hz) and for a fine frequency resolution. The PLL occupies 0.09-mm 2 core area and exhibits 220 fs rms jitter while consuming 25 mW, giving FoM RMS of â239 dB. Its frequency acquisition time improves from 780 to 45 Ξs with the gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channels{\textquoteright} frequencies of IEEE-802.11ad, allows a transmitter (TX) error vector magnitude (EVM) down to â35.9 dB assuming a TX signal to the noise-plus-distortion ratio (SNDR) of 40 dB, and, thus, is capable of supporting 256 quadrature amplitude modulation (QAM).
Tsai, C-H, Zong, Z, Pepe, F, Mangraviti, G, Craninckx, J & Wambacq, P 2020, 'Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication', IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 55, no. 7, 9097192, pp. 1854-1863. https://doi.org/10.1109/JSSC.2020.2993717
Tsai, C.-H., Zong, Z., Pepe, F., Mangraviti, G., Craninckx, J., & Wambacq, P. (2020). Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 55(7), 1854-1863. Article 9097192. https://doi.org/10.1109/JSSC.2020.2993717
@article{da3b1082fc4441adb4c91f7ebabfea13,
title = "Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication",
abstract = "This article analyses and demonstrates a 22.5â27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of the automatic bandwidth control, on the effect of the gear-shift algorithm for fast lock and on the different noise contributions. The proposed gear-shift algorithm scales up the PLL bandwidth for faster acquisition and orderly reduces it for jitter performance. The PLL contains a digitally controlled oscillator (DCO) based on transformer feedback with a tunable source-bridged capacitor, which allows for a low phase noise (PN) over a wide tuning range (FoM of â184 dBc/Hz and FoM T of â191 dBc/Hz) and for a fine frequency resolution. The PLL occupies 0.09-mm 2 core area and exhibits 220 fs rms jitter while consuming 25 mW, giving FoM RMS of â239 dB. Its frequency acquisition time improves from 780 to 45 Ξs with the gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channels{\textquoteright} frequencies of IEEE-802.11ad, allows a transmitter (TX) error vector magnitude (EVM) down to â35.9 dB assuming a TX signal to the noise-plus-distortion ratio (SNDR) of 40 dB, and, thus, is capable of supporting 256 quadrature amplitude modulation (QAM).",
keywords = "CMOS",
author = "Cheng-Hsueh Tsai and Zhiwei Zong and Federico Pepe and Giovanni Mangraviti and Jan Craninckx and Piet Wambacq",
year = "2020",
month = may,
day = "20",
doi = "10.1109/JSSC.2020.2993717",
language = "English",
volume = "55",
pages = "1854--1863",
journal = "IEEE JOURNAL OF SOLID-STATE CIRCUITS",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "7",
}