In this work, we present time-zero variability and degradation data obtained from a large set of on-chip devices in specifically designed arrays, from room temperature to 4K. We show that the investigated nMOS transistors still suffer from significant PBTI and HC degradation down to the lowest temperatures. We further investigate the contribution of multiple-carrier mechanism versus single-carrier mechanism of Si-H bond dissociation across different temperatures. Finally, we extrapolate the time-to-failure for a large gate and drain bias space and show that HCD after on-state stress and off-state stress show opposite temperature trends with the off-state stress being worse at cryogenic temperatures.
Grill, A, Bury, E, Michl, J, Tyaginov, S, Linten, D, Grasser, T, Parvais, B, Kaczer, B, Waltl, M & Radu, I 2020, Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures. in 2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings., 9128316, IEEE International Reliability Physics Symposium Proceedings, vol. 2020-April, Institute of Electrical and Electronics Engineers Inc., pp. 1-6, 2020 IEEE International Reliability Physics Symposium, IRPS 2020, Virtual, Online, United States, 28/04/20. https://doi.org/10.1109/IRPS45951.2020.9128316
Grill, A., Bury, E., Michl, J., Tyaginov, S., Linten, D., Grasser, T., Parvais, B., Kaczer, B., Waltl, M., & Radu, I. (2020). Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures. In 2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings (pp. 1-6). Article 9128316 (IEEE International Reliability Physics Symposium Proceedings; Vol. 2020-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS45951.2020.9128316
@inproceedings{a40971b1606a4d46bdd6048bf1c5c349,
title = "Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures",
abstract = "In this work, we present time-zero variability and degradation data obtained from a large set of on-chip devices in specifically designed arrays, from room temperature to 4K. We show that the investigated nMOS transistors still suffer from significant PBTI and HC degradation down to the lowest temperatures. We further investigate the contribution of multiple-carrier mechanism versus single-carrier mechanism of Si-H bond dissociation across different temperatures. Finally, we extrapolate the time-to-failure for a large gate and drain bias space and show that HCD after on-state stress and off-state stress show opposite temperature trends with the off-state stress being worse at cryogenic temperatures.",
keywords = "28 nm bulk CMOS, 4K, Bias Temperature Instability (BTI), Cryoelectronics, Cryogenic, Degradation Maps, Hot Carrier Degradation (HCD), Smart Arrays, Variability",
author = "A. Grill and E. Bury and J. Michl and S. Tyaginov and D. Linten and T. Grasser and B. Parvais and B. Kaczer and M. Waltl and I. Radu",
year = "2020",
month = apr,
doi = "10.1109/IRPS45951.2020.9128316",
language = "English",
series = "IEEE International Reliability Physics Symposium Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--6",
booktitle = "2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings",
address = "United States",
note = "2020 IEEE International Reliability Physics Symposium, IRPS 2020 ; Conference date: 28-04-2020 Through 30-05-2020",
}