We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoMT of -191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.
Tsai, CH, Pepe, F, Mangraviti, G, Zong, Z, Craninckx, J & Wambacq, P 2019, A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference., 8902868, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 111-114, 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, 23/09/19. https://doi.org/10.1109/ESSCIRC.2019.8902868
Tsai, C. H., Pepe, F., Mangraviti, G., Zong, Z., Craninckx, J., & Wambacq, P. (2019). A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (pp. 111-114). Article 8902868 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC.2019.8902868
@inproceedings{92837a21d76f4350ae631d1df5b68cbe,
title = "A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter",
abstract = "We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoMT of -191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.",
keywords = "Fast-lock phase-locked loop (PLL), IEEE 802.11ad, mm-wave",
author = "Tsai, {Cheng Hsueh} and Federico Pepe and Giovanni Mangraviti and Zhiwei Zong and Jan Craninckx and Piet Wambacq",
year = "2019",
month = sep,
day = "1",
doi = "10.1109/ESSCIRC.2019.8902868",
language = "English",
series = "ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "111--114",
booktitle = "ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference",
address = "United States",
note = "45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 ; Conference date: 23-09-2019 Through 26-09-2019",
}