Markulic, N., Renukaswamy, P. T., Martens, E., van Liempd, B., Wambacq, P., & Craninckx, J. (2019). A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With-41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE Journal of Solid-State Circuits, 54(4), 1059-1073. Article 8629048. https://doi.org/10.1109/JSSC.2018.2886324

@article{6b41a3844fb9407c93fde8ee2aaffaa1,
title = "A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With-41.3-dB EVM at 1024 QAM in 28-nm CMOS",
abstract = "We present a subsampling polar transmitter (SSPTX) in 28-nm CMOS that consists of a low-noise phase modulating (PM) digital subsampling phase-locked loop (PLL) and a harmonic rejection mixed (HRM) inverse-class-D (D -1 ) digital power amplifier (DPA) for amplitude modulation (AM). The DPA is, unlike in a typical polar transmitter (TX), placed within the PLL and the phase-error detection happens directly at the DPA output. The subsampling polar TX thus becomes sensitive not only to phase errors but also to modulation amplitude. That feature enables AM-AM and PM-PM distortion to be detected and cancelled digitally in the background, while the transmitter operates normally. Moreover, the AM-PM cross distortion is filtered by the loop itself. The chip operates from a 0.9-V supply at 5.5 GHz with 2.5 MHz BW (1024 QAM) with average 1.1-dBm output power and total power consumption of 50 mW.",
keywords = "Background calibration, digital-to-time converter (DTC), linearization, phase-locked loop (PLL), polar transmitter, subsampling, transmitter",
author = "Nereo Markulic and Renukaswamy, {Pratap Tumkur} and Ewout Martens and {van Liempd}, Barend and Piet Wambacq and Jan Craninckx",
year = "2019",
month = apr,
doi = "10.1109/JSSC.2018.2886324",
language = "English",
volume = "54",
pages = "1059--1073",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",
}