3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic Vthtuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ∼103mV/V and ∼139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the ION performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.
Vandooren, A, Wu, Z, Khaled, A, Franco, J, Parvais, B, Li, W, Witters, L, Walke, A, Peng, L, Rassoul, N, Matagne, P, Debruyn, H, Jamieson, G, Inoue, F, Devriendt, K, Teugels, L, Heylen, N, Vecchio, E, Zheng, T, Radisic, D, Rosseel, E, Vanherle, W, Hikavyy, A, Chan, BT, Besnard, G, Schwarzenbach, W, Gaudin, G, Radu, I, Nguyen, BY, Waldron, N, De Heyn, V, Demuynck, S, Boemmels, J, Ryckaert, J, Collaert, N & Mocuta, D 2019, Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications. in 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers., 8776490, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. T56-T57, 39th Symposium on VLSI Technology, VLSI Technology 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIT.2019.8776490
Vandooren, A., Wu, Z., Khaled, A., Franco, J., Parvais, B., Li, W., Witters, L., Walke, A., Peng, L., Rassoul, N., Matagne, P., Debruyn, H., Jamieson, G., Inoue, F., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., Zheng, T., ... Mocuta, D. (2019). Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers (pp. T56-T57). Article 8776490 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2019.8776490
@inproceedings{9d23abbb46b842e8aed0355659148430,
title = "Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications",
abstract = "3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic Vthtuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ∼103mV/V and ∼139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the ION performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.",
author = "A. Vandooren and Z. Wu and A. Khaled and J. Franco and B. Parvais and W. Li and L. Witters and A. Walke and L. Peng and N. Rassoul and P. Matagne and H. Debruyn and G. Jamieson and F. Inoue and K. Devriendt and L. Teugels and N. Heylen and E. Vecchio and T. Zheng and D. Radisic and E. Rosseel and W. Vanherle and A. Hikavyy and Chan, {B. T.} and G. Besnard and W. Schwarzenbach and G. Gaudin and I. Radu and Nguyen, {B. Y.} and N. Waldron and {De Heyn}, V. and S. Demuynck and J. Boemmels and J. Ryckaert and N. Collaert and D. Mocuta",
year = "2019",
month = jun,
day = "1",
doi = "10.23919/VLSIT.2019.8776490",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "T56--T57",
booktitle = "2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers",
address = "United States",
note = "39th Symposium on VLSI Technology, VLSI Technology 2019 ; Conference date: 09-06-2019 Through 14-06-2019",
}