Complexity measurement, essential in diverse fields like finance, biomedicine, climate science, and network traffic, demands real-time computation to mitigate risks and losses. Sample Entropy (SampEn) is an efficacious metric which quantifies the complexity by assessing the similarities among microscale patterns within the time-series data. Unfortunately, the conventional implementation of SampEn is computationally demanding, posing challenges for its application in real-time analysis, particularly for long time series. Field Programmable Gate Arrays (FPGAs) offer a promising solution due to their fast processing and energy efficiency, which can be customized to perform specific signal processing tasks directly in hardware. The presented work focuses on accelerating SampEn analysis on FPGAs for efficient time-series complexity analysis. A refined, fast, Lightweight SampEn architecture (LW SampEn) on FPGA, which is optimized to use sorted sequences to reduce computational complexity, is accelerated for FPGAs. Various sorting algorithms on FPGAs are assessed, and novel dynamic loop strategies and microarchitectures are proposed to tackle SampEn{\textquoteright}s undetermined search boundaries. Multi-source biomedical signals are used to profile the above design and select a proper architecture, underscoring the importance of customizing FPGA design for specific applications. Our optimized architecture achieves a 7x to 560x speedup over standard baseline architecture, enabling real-time processing of time-sensitive data.
Chen, C, Liu, C, Li, J & da Silva, B 2024, 'Acceleration of Fast Sample Entropy for FPGAs', IEEE Transactions on Computers, pp. 1-14. https://doi.org/10.1109/TC.2024.3457735
Chen, C., Liu, C., Li, J., & da Silva, B. (2024). Acceleration of Fast Sample Entropy for FPGAs. IEEE Transactions on Computers, 1-14. Article 1. https://doi.org/10.1109/TC.2024.3457735
@article{b717f1f9612d4b88a2d17a028da163f3,
title = "Acceleration of Fast Sample Entropy for FPGAs",
abstract = "Complexity measurement, essential in diverse fields like finance, biomedicine, climate science, and network traffic, demands real-time computation to mitigate risks and losses. Sample Entropy (SampEn) is an efficacious metric which quantifies the complexity by assessing the similarities among microscale patterns within the time-series data. Unfortunately, the conventional implementation of SampEn is computationally demanding, posing challenges for its application in real-time analysis, particularly for long time series. Field Programmable Gate Arrays (FPGAs) offer a promising solution due to their fast processing and energy efficiency, which can be customized to perform specific signal processing tasks directly in hardware. The presented work focuses on accelerating SampEn analysis on FPGAs for efficient time-series complexity analysis. A refined, fast, Lightweight SampEn architecture (LW SampEn) on FPGA, which is optimized to use sorted sequences to reduce computational complexity, is accelerated for FPGAs. Various sorting algorithms on FPGAs are assessed, and novel dynamic loop strategies and microarchitectures are proposed to tackle SampEn{\textquoteright}s undetermined search boundaries. Multi-source biomedical signals are used to profile the above design and select a proper architecture, underscoring the importance of customizing FPGA design for specific applications. Our optimized architecture achieves a 7x to 560x speedup over standard baseline architecture, enabling real-time processing of time-sensitive data.",
author = "Chao Chen and Chengyu Liu and Jianqing Li and {da Silva}, Bruno",
note = "Funding Information: This research was funded by the National Natural Science Foundation of China (62171123, 62071241, 62201144 and 62211530112). Chao Chen, Jianqing Li, Chengyu Liu are with the School of Instrument Science and Engineering, Southeast University, Nanjing 210096, China Chao Chen, Bruno da Silva are with Department of Electronics and Informatics (ETRO), Vrije Universiteit Brussel (VUB), 1050 Brussels, Belgium Chengyu Liu, Jianqing Li, and Bruno da Silva are co-corresponding authors, e-mail: (chengyu@seu.edu.cn, ljq@seu.edu.cn, bdasilva@etrovub.be) Publisher Copyright: {\textcopyright} 1968-2012 IEEE.",
year = "2024",
month = sep,
day = "1",
doi = "10.1109/TC.2024.3457735",
language = "English",
pages = "1--14",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE",
}