Vandooren, A., Franco, J., Wu, Z., Parvais, B., Li, W., Witters, L., Walke, A., Peng, L., Deshpande, V., Rassoul, N., Hellings, G., Jamieson, G., Inoue, F., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., Zheng, T., Rosseel, E., ... Collaert, N. (2019). First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers. In 2018 IEEE International Electron Devices Meeting, IEDM 2018 (pp. 7.1.1-7.1.4). Article 8614654 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2018.8614654

@inproceedings{1d24d7dfba8e4c69ba1868aacc86a30a,
title = "First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers",
abstract = " 3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature ( T 525 C) in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature. ",
author = "A. Vandooren and J. Franco and Z. Wu and B. Parvais and W. Li and L. Witters and A. Walke and L. Peng and V. Deshpande and N. Rassoul and G. Hellings and G. Jamieson and F. Inoue and K. Devriendt and L. Teugels and N. Heylen and E. Vecchio and T. Zheng and E. Rosseel and W. Vanherle and A. Hikavyy and G. Mannaert and Chan, {B. T.} and R. Ritzenthaler and J. Mitard and L. Ragnarsson and N. Waldron and {De Heyn}, V. and S. Demuynck and J. Boemmels and D. Mocuta and J. Ryckaert and N. Collaert",
year = "2019",
month = jan,
day = "16",
doi = "10.1109/IEDM.2018.8614654",
language = "English",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "7.1.1--7.1.4",
booktitle = "2018 IEEE International Electron Devices Meeting, IEDM 2018",
address = "United States",
note = "64th Annual IEEE International Electron Devices Meeting, IEDM 2018 ; Conference date: 01-12-2018 Through 05-12-2018",
}