In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Junction-less devices are shown to be attractive top tier devices for low temperature processing, low complexity of fabrication and meeting reliability specification despite without the use of 'reliability' anneal. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.
Vandooren, A, Witters, L, Franco, J, Mallik, A, Parvais, B, Wu, Z, Li, W, Rosseel, E, Hikkavyy, A, Peng, L, Rassoul, N, Jamieson, G, Inoue, F, Verbinnen, G, Devriendt, K, Teugels, L, Heylen, N, Vecchio, E, Zheng, T, Waldron, N, Boemmels, J, De Heyn, V, Mocuta, D, Ryckaert, J & Collaert, N 2019, Key challenges and opportunities for 3D sequential integration. in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018., 8640203, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Burlingame, United States, 15/10/18. https://doi.org/10.1109/S3S.2018.8640203
Vandooren, A., Witters, L., Franco, J., Mallik, A., Parvais, B., Wu, Z., Li, W., Rosseel, E., Hikkavyy, A., Peng, L., Rassoul, N., Jamieson, G., Inoue, F., Verbinnen, G., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., Zheng, T., ... Collaert, N. (2019). Key challenges and opportunities for 3D sequential integration. In 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 Article 8640203 (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2018.8640203
@inproceedings{0d81977f09d0408483f370638db5bc7f,
title = "Key challenges and opportunities for 3D sequential integration",
abstract = "In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Junction-less devices are shown to be attractive top tier devices for low temperature processing, low complexity of fabrication and meeting reliability specification despite without the use of 'reliability' anneal. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.",
keywords = "3D sequential, Junctionless, Silicon-on-insulator, Thermal budget, Wafer bonding",
author = "A. Vandooren and L. Witters and J. Franco and A. Mallik and B. Parvais and Z. Wu and W. Li and E. Rosseel and A. Hikkavyy and L. Peng and N. Rassoul and G. Jamieson and F. Inoue and G. Verbinnen and K. Devriendt and L. Teugels and N. Heylen and E. Vecchio and T. Zheng and N. Waldron and J. Boemmels and {De Heyn}, V. and D. Mocuta and J. Ryckaert and N. Collaert",
year = "2019",
month = feb,
day = "11",
doi = "10.1109/S3S.2018.8640203",
language = "English",
series = "2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018",
address = "United States",
note = "2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 ; Conference date: 15-10-2018 Through 18-10-2018",
}