Xiang, Y., Verhulst, A. S., Yakimets, D., Parvais, B., Mocuta, A., & Groeseneken, G. (2019). Process-Induced Power-Performance Variability in Sub-5-nm III–V Tunnel FETs. IEEE Transactions on Electron Devices, 66(6), 2802-2808. Article 8689112. https://doi.org/10.1109/TED.2019.2909217

@article{975ad200d9814e54acb003594bfb23eb,
title = "Process-Induced Power-Performance Variability in Sub-5-nm III–V Tunnel FETs",
abstract = "We examine the power-performance variability of a projected sub-5-nm GaAsSb/InGaAs vertical tunnel FET considering various process control tolerances in the state-of-the-art device integration and propose countermeasures in device design. Nominal and three-sigma-corner device characteristics generated in quantum-mechanical/TCAD simulations are used to calibrate a semiempirical compact model, based on which the nominal and variability-inclusive energy-delay landscapes are extracted from ring-oscillator circuit simulations at sub-500-mV supply voltages. Variations in four parameters are identified as of major impact on the worst-case speed loss and iso-speed energy penalty: dopant pocket thickness, gate work function, hetero-band offset, and body thickness (in descending order). Variability-resilient device options are explored against pocket thickness variation, including: 1) pocket desensitization with increased thickness and reduced doping concentration and 2) broken-gap tunnel FET with a negative effective band gap. Reengineered devices achieve < 18 × speed loss and < 3 × energy penalty for (0.1-1) ns gate delay with respect to the nominal corner.",
author = "Yang Xiang and Verhulst, {Anne S.} and Dmitry Yakimets and Bertrand Parvais and Anda Mocuta and Guido Groeseneken",
year = "2019",
month = jun,
doi = "10.1109/TED.2019.2909217",
language = "English",
volume = "66",
pages = "2802--2808",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",
}