3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at V G= V th+ 0.6 V, 125 °C), even without the use of 'reliability' anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.
Vandooren, A, Franco, J, Parvais, B, Wu, Z, Witters, L, Walke, A, Li, W, Peng, L, Deshpande, V, Bufler, FM, Rassoul, N, Hellings, G, Jamieson, G, Inoue, F, Verbinnen, G, Devriendt, K, Teugels, L, Heylen, N, Vecchio, E, Zheng, T, Rosseel, E, Vanherle, W, Hikavyy, A, Chan, BT, Ritzenthaler, R, Besnard, G, Schwarzenbach, W, Gaudin, G, Radu, I, Nguyen, BY, Waldron, N, De Heyn, V, Mocuta, D & Collaert, N 2018, '3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability', IEEE Transactions on Electron Devices, vol. 65, no. 11, 8487028, pp. 5165-5171. https://doi.org/10.1109/TED.2018.2871265
Vandooren, A., Franco, J., Parvais, B., Wu, Z., Witters, L., Walke, A., Li, W., Peng, L., Deshpande, V., Bufler, F. M., Rassoul, N., Hellings, G., Jamieson, G., Inoue, F., Verbinnen, G., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., ... Collaert, N. (2018). 3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability. IEEE Transactions on Electron Devices, 65(11), 5165-5171. Article 8487028. https://doi.org/10.1109/TED.2018.2871265
@article{cfb3b0ed213a4c73a9651e0d11344d6f,
title = "3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability",
abstract = "3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at V G= V th+ 0.6 V, 125 °C), even without the use of 'reliability' anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer. ",
keywords = "3-D sequential, analog, Annealing, Bonding, Doping, junctionless (JL) devices, Logic gates, low-temperature CMOS, matching, MOS devices, Reliability, RF, Silicon, silicon-on-insulator (SOI), wafer bonding.",
author = "A. Vandooren and J. Franco and B. Parvais and Z. Wu and L. Witters and A. Walke and W. Li and L. Peng and V. Deshpande and Bufler, {F. M.} and N. Rassoul and G. Hellings and G. Jamieson and F. Inoue and G. Verbinnen and K. Devriendt and L. Teugels and N. Heylen and E. Vecchio and T. Zheng and E. Rosseel and W. Vanherle and A. Hikavyy and Chan, {B. T.} and R. Ritzenthaler and G. Besnard and W. Schwarzenbach and G. Gaudin and I. Radu and Nguyen, {B. Y.} and N. Waldron and {De Heyn}, V. and D. Mocuta and N. Collaert",
year = "2018",
month = nov,
doi = "10.1109/TED.2018.2871265",
language = "English",
volume = "65",
pages = "5165--5171",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "11",
}