3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.
Vandooren, A, Franco, J, Parvais, B, Wu, Z, Witters, L, Walke, A, Li, W, Peng, L, Desphande, V, Bufler, FM, Rassoul, N, Hellings, G, Jamieson, G, Inoue, F, Verbinnen, G, Devriendt, K, Teugels, L, Heylen, N, Vecchio, E, Zheng, T, Rosseel, E, Vanherle, W, Hikavyy, A, Chan, BT, Ritzenthaler, R, Besnard, G, Schwarzenbach, W, Gaudin, G, Radu, I, Nguyen, BY, Waldron, N, Heyn, VD, Mocuta, D & Collaert, N 2018, 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510705, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 69-70, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIT.2018.8510705
Vandooren, A., Franco, J., Parvais, B., Wu, Z., Witters, L., Walke, A., Li, W., Peng, L., Desphande, V., Bufler, F. M., Rassoul, N., Hellings, G., Jamieson, G., Inoue, F., Verbinnen, G., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., ... Collaert, N. (2018). 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 69-70). Article 8510705 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510705
@inproceedings{0a8e7ac7981a4fdca05ce5bfb0e77e4f,
title = "3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability",
abstract = "3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.",
author = "A. Vandooren and J. Franco and B. Parvais and Z. Wu and L. Witters and A. Walke and W. Li and L. Peng and V. Desphande and Bufler, {F. M.} and N. Rassoul and G. Hellings and G. Jamieson and F. Inoue and G. Verbinnen and K. Devriendt and L. Teugels and N. Heylen and E. Vecchio and T. Zheng and E. Rosseel and W. Vanherle and A. Hikavyy and Chan, {B. T.} and R. Ritzenthaler and G. Besnard and W. Schwarzenbach and G. Gaudin and I. Radu and Nguyen, {B. Y.} and N. Waldron and Heyn, {V. De} and D. Mocuta and N. Collaert",
year = "2018",
month = oct,
day = "25",
doi = "10.1109/VLSIT.2018.8510705",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "69--70",
booktitle = "2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018",
address = "United States",
note = "38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 ; Conference date: 18-06-2018 Through 22-06-2018",
}