An in-depth study of scaled nanowire Ge pFETs for digital and analog applications is proposed. Improved device characteristics are first obtained after gaining a good understanding of the HPA on device performance. Up to 45% higher ID,SAT is obtained at IOFF=3nA/fin when comparing to best Si GAA nFET and similar ID,SAT is found when benchmarking to mature 14/16nm pFinFET technology at-0.5 VDD. The temperature dependent study of ID,SAT highlights that the mechanism limiting the transport in Ge at short channel are neither purely diffusive nor fully ballistic.
Mitard, J, Jang, D, Eneman, G, Arimura, H, Parvais, B, Richard, O, Van Marcke, P, Witters, L, Capogreco, E, Bender, H, Ritzenthaler, R, Mertens, H, Hikavyy, A, Loo, R, Dekkers, H, Sebaai, F, Milenin, A, Horiguchi, N, Mocuta, A, Mocuta, D & Collaert, N 2018, An in-depth study of high-performing strained germanium nanowires pFETs. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510666, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 83-84, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIT.2018.8510666
Mitard, J., Jang, D., Eneman, G., Arimura, H., Parvais, B., Richard, O., Van Marcke, P., Witters, L., Capogreco, E., Bender, H., Ritzenthaler, R., Mertens, H., Hikavyy, A., Loo, R., Dekkers, H., Sebaai, F., Milenin, A., Horiguchi, N., Mocuta, A., ... Collaert, N. (2018). An in-depth study of high-performing strained germanium nanowires pFETs. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 83-84). Article 8510666 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510666
@inproceedings{fd2fd4c76c484be18b3173957e7fa6c2,
title = "An in-depth study of high-performing strained germanium nanowires pFETs",
abstract = "An in-depth study of scaled nanowire Ge pFETs for digital and analog applications is proposed. Improved device characteristics are first obtained after gaining a good understanding of the HPA on device performance. Up to 45% higher ID,SAT is obtained at IOFF=3nA/fin when comparing to best Si GAA nFET and similar ID,SAT is found when benchmarking to mature 14/16nm pFinFET technology at-0.5 VDD. The temperature dependent study of ID,SAT highlights that the mechanism limiting the transport in Ge at short channel are neither purely diffusive nor fully ballistic.",
author = "J. Mitard and D. Jang and G. Eneman and H. Arimura and B. Parvais and O. Richard and {Van Marcke}, P. and L. Witters and E. Capogreco and H. Bender and R. Ritzenthaler and H. Mertens and A. Hikavyy and R. Loo and H. Dekkers and F. Sebaai and A. Milenin and N. Horiguchi and A. Mocuta and D. Mocuta and N. Collaert",
year = "2018",
month = oct,
day = "25",
doi = "10.1109/VLSIT.2018.8510666",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "83--84",
booktitle = "2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018",
address = "United States",
note = "38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 ; Conference date: 18-06-2018 Through 22-06-2018",
}