Achieving high linearity and bandwidth with good power efficiency makes the design of ADCs in deep nanoscale CMOS processes very challenging, as the constraints of low-voltage operation and limited intrinsic gain often dictate the use of power-consuming analog circuits and intensive digital calibration. This paper addresses these problems by introducing a pipelined ADC that exploits the low but very constant open-loop gain versus output voltage characteristic of the ring amplifier (ringamp) to achieve both high speed and linearity in low-voltage nanoscale CMOS designs. A tunable ringamp biasing scheme using an anti-parallel arrangement of CMOS transistors and an active ringamp-based common-mode feedback are also introduced. A single-channel prototype ADC is implemented in a standard 28-nm CMOS process, achieving 58.7-dB SNDR and 72.4-dB SFDR at 600 MS/s while consuming 14.5 mW from a single 0.9-V supply, resulting in Walden and Schreier figure-of-merit (FoM) values of 34.4 fJ/conv.-step and 161.9 dB, respectively.
Lagos Benites, JL, Hershberg, B, Martens, E, Wambacq, P & Craninckx, J 2018, 'A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS', IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 54, no. 2, 8551268, pp. 403-416. https://doi.org/10.1109/JSSC.2018.2879923
Lagos Benites, J. L., Hershberg, B., Martens, E., Wambacq, P., & Craninckx, J. (2018). A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 54(2), 403-416. Article 8551268. https://doi.org/10.1109/JSSC.2018.2879923
@article{c82026ee552c42d2a035a22ea04adfe4,
title = "A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS",
abstract = "Achieving high linearity and bandwidth with good power efficiency makes the design of ADCs in deep nanoscale CMOS processes very challenging, as the constraints of low-voltage operation and limited intrinsic gain often dictate the use of power-consuming analog circuits and intensive digital calibration. This paper addresses these problems by introducing a pipelined ADC that exploits the low but very constant open-loop gain versus output voltage characteristic of the ring amplifier (ringamp) to achieve both high speed and linearity in low-voltage nanoscale CMOS designs. A tunable ringamp biasing scheme using an anti-parallel arrangement of CMOS transistors and an active ringamp-based common-mode feedback are also introduced. A single-channel prototype ADC is implemented in a standard 28-nm CMOS process, achieving 58.7-dB SNDR and 72.4-dB SFDR at 600 MS/s while consuming 14.5 mW from a single 0.9-V supply, resulting in Walden and Schreier figure-of-merit (FoM) values of 34.4 fJ/conv.-step and 161.9 dB, respectively.",
keywords = "Active common-mode feedback (CMFB), gain calibration, pipelined ADC, ring amplifier (ringamp), single channel",
author = "{Lagos Benites}, {Jorge Luis} and Benjamin Hershberg and Ewout Martens and Piet Wambacq and Jan Craninckx",
year = "2018",
month = nov,
day = "28",
doi = "10.1109/JSSC.2018.2879923",
language = "English",
volume = "54",
pages = "403--416",
journal = "IEEE JOURNAL OF SOLID-STATE CIRCUITS",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",
}