Mattia, O. E., Guermandi, D., Torfs, G., & Wambacq, P. (2018). Comparator hysteresis compensation for decision feedback equalizers. Electronics Letters, 54(25), 1421-1422. https://doi.org/10.1049/el.2018.6485

@article{a9f95fc3ac754e868ae500c4e0d5bb86,
title = "Comparator hysteresis compensation for decision feedback equalizers",
abstract = "High-speed comparators are extensively used in serial link receiver designs. Some comparator architectures can show significant hysteresis that degrade the sensitivity of the receiver, increasing the bit error rate. In this Letter, a comparator hysteresis compensation strategy that re-uses the first tap of a decision feedback equaliser to shift the comparator input voltage, increasing the decision margin is proposed. An updated equaliser coefficient adaptation scheme is also introduced. The proposed technique can be used for binary and multi-level modulations.",
keywords = "compensation, decision feedback equalisers, hysteresis, comparators (circuits), decision feedback equaliser, serial link receiver designs, bit error rate, decision margin, equaliser coefficient adaptation scheme, comparator input voltage architectures, high-speed comparator hysteresis compensation strategy, multilevel modulations, binary modulations",
author = "Mattia, {Oscar Elisio} and Davide Guermandi and Guy Torfs and Piet Wambacq",
year = "2018",
month = dec,
day = "17",
doi = "10.1049/el.2018.6485",
language = "English",
volume = "54",
pages = "1421--1422",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology",
number = "25",
}