A new platform for Memory periphery device based on FinFET technology is proposed, targeting DRAM technology node 1Y and beyond. Up to 30% power saving is demonstrated at system level with respect to a conventional planar SiON based solution, thanks to an optimized cost-effective process flow (38% less expensive than equivalent logic flow), compatible with a DRAM technology. This makes the solution perfectly suitable for low power mobile applications or enabling faster server applications. The additional sensing margin can be used to aggressively reduce the analog area (>50%) or to mitigate the process concern on the memory array, paving the way for the introduction of different storage elements. An overview of the device characteristics based on the fabricated hardware is presented, exploring potential knobs to further improve the transistors.
Spessot, A, Sharan, N, Oh, H, Ritzenthaler, R, Litta, ED, O'Sullivan, B, Mallik, A, De Keersgieter, A, Parvais, B, Sherazi, Y, Machkaoutsan, V, Kim, C, Fazan, P, Mocuta, D, Mocuta, A & Horiguchi, N 2018, Cost Effective FinFET Platform for Stand Alone DRAM 1Y and beyond Memory Periphery. in 2018 IEEE 10th International Memory Workshop, IMW 2018. Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 10th IEEE International Memory Workshop, IMW 2018, Kyoto, Japan, 13/05/18. https://doi.org/10.1109/IMW.2018.8388823
Spessot, A., Sharan, N., Oh, H., Ritzenthaler, R., Litta, E. D., O'Sullivan, B., Mallik, A., De Keersgieter, A., Parvais, B., Sherazi, Y., Machkaoutsan, V., Kim, C., Fazan, P., Mocuta, D., Mocuta, A., & Horiguchi, N. (2018). Cost Effective FinFET Platform for Stand Alone DRAM 1Y and beyond Memory Periphery. In 2018 IEEE 10th International Memory Workshop, IMW 2018 (pp. 1-4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IMW.2018.8388823
@inproceedings{ef9547f05372445faf3c7f244f14bc62,
title = "Cost Effective FinFET Platform for Stand Alone DRAM 1Y and beyond Memory Periphery",
abstract = "A new platform for Memory periphery device based on FinFET technology is proposed, targeting DRAM technology node 1Y and beyond. Up to 30% power saving is demonstrated at system level with respect to a conventional planar SiON based solution, thanks to an optimized cost-effective process flow (38% less expensive than equivalent logic flow), compatible with a DRAM technology. This makes the solution perfectly suitable for low power mobile applications or enabling faster server applications. The additional sensing margin can be used to aggressively reduce the analog area (>50%) or to mitigate the process concern on the memory array, paving the way for the introduction of different storage elements. An overview of the device characteristics based on the fabricated hardware is presented, exploring potential knobs to further improve the transistors.",
keywords = "DRAM, FinFET, HKMG, peripheral transistors",
author = "Alessio Spessot and Neha Sharan and Hyungrock Oh and Romain Ritzenthaler and Litta, {Eugenio Dentoni} and Barry O'Sullivan and Arindam Mallik and {De Keersgieter}, An and Bertrand Parvais and Yasser Sherazi and Vladimir Machkaoutsan and Cheolgyu Kim and Pierre Fazan and Dan Mocuta and Anda Mocuta and Naoto Horiguchi",
year = "2018",
month = jun,
day = "19",
doi = "10.1109/IMW.2018.8388823",
language = "English",
pages = "1--4",
booktitle = "2018 IEEE 10th International Memory Workshop, IMW 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",
note = "10th IEEE International Memory Workshop, IMW 2018 ; Conference date: 13-05-2018 Through 16-05-2018",
}