Yakimets, D., Garcia Bardon, M., Jang, D., Schuddinck, P., Sherazi, Y., Weckx, P., Miyaguchi, K., Parvais, B., Raghavan, P., Spessot, A., Verkest, D., & Mocuta, A. (2018). Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology. In 2017 IEEE International Electron Devices Meeting, IEDM 2017 (pp. 20.4.1-20.4.4). (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2017.8268429

@inproceedings{b7ef0be6679f4e8e9af7c93de851d7c9,
title = "Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology",
abstract = "In this paper, we show how 5.5 tracks standard cells can be enabled at gate pitch 42 nm and metal pitch 21 nm and achieve 60% active power reduction from the 7nm node. A device downselection methodology driven by power and performance targets is introduced. This method demonstrates that three stacked nanosheets of 20 nm width are competitive with FinFETs made with two fins while relaxing the constraints on layout design rules.",
author = "D. Yakimets and {Garcia Bardon}, M. and D. Jang and P. Schuddinck and Y. Sherazi and P. Weckx and K. Miyaguchi and B. Parvais and P. Raghavan and A. Spessot and D. Verkest and A. Mocuta",
year = "2018",
month = jan,
day = "23",
doi = "10.1109/IEDM.2017.8268429",
language = "English",
isbn = "9781538635599",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "20.4.1--20.4.4",
booktitle = "2017 IEEE International Electron Devices Meeting, IEDM 2017",
address = "United States",
note = "63rd IEEE International Electron Devices Meeting, IEDM 2017 ; Conference date: 02-12-2017 Through 06-12-2017",
}