The continued physical feature size scaling of CMOS transistors is experiencing asperities due to several factors (physical, technological, and economical), and it is expected to reach its boundary in the coming years. Sequential-3D (S3D) integration has been perceived as a promising alternative to continue the benefits offered by semiconductor scaling. This paper addresses the different variants of S3D integration and potential challenges to achieve a realizable solution. We analyze and quantify the benefits observed due to sequential scaling at a die level.
Mallik, A, Vandooren, A, Witters, L, Walke, A, Franco, J, Sherazi, Y, Weckx, P, Yakimets, D, Bardon, M, Parvais, B, Debacker, P, Ku, BW, Lim, SK, Mocuta, A, Mocuta, D, Ryckaert, J, Collaert, N & Raghavan, P 2018, The impact of sequential-3D integration on semiconductor scaling roadmap. in 2017 IEEE International Electron Devices Meeting, IEDM 2017. Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., pp. 32.1.1-32.1.4, 63rd IEEE International Electron Devices Meeting, IEDM 2017, San Francisco, United States, 2/12/17. https://doi.org/10.1109/IEDM.2017.8268483
Mallik, A., Vandooren, A., Witters, L., Walke, A., Franco, J., Sherazi, Y., Weckx, P., Yakimets, D., Bardon, M., Parvais, B., Debacker, P., Ku, B. W., Lim, S. K., Mocuta, A., Mocuta, D., Ryckaert, J., Collaert, N., & Raghavan, P. (2018). The impact of sequential-3D integration on semiconductor scaling roadmap. In 2017 IEEE International Electron Devices Meeting, IEDM 2017 (pp. 32.1.1-32.1.4). (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2017.8268483
@inproceedings{51c5fb305f634e47aa9b0ca1f515c2f9,
title = "The impact of sequential-3D integration on semiconductor scaling roadmap",
abstract = "The continued physical feature size scaling of CMOS transistors is experiencing asperities due to several factors (physical, technological, and economical), and it is expected to reach its boundary in the coming years. Sequential-3D (S3D) integration has been perceived as a promising alternative to continue the benefits offered by semiconductor scaling. This paper addresses the different variants of S3D integration and potential challenges to achieve a realizable solution. We analyze and quantify the benefits observed due to sequential scaling at a die level.",
keywords = "Cost of ownership, Design Technology Cointegration, Integration, Sequential 3D",
author = "A. Mallik and A. Vandooren and L. Witters and A. Walke and J. Franco and Y. Sherazi and P. Weckx and D. Yakimets and M. Bardon and B. Parvais and P. Debacker and Ku, {B. W.} and Lim, {S. K.} and A. Mocuta and D. Mocuta and J. Ryckaert and N. Collaert and P. Raghavan",
year = "2018",
month = jan,
day = "23",
doi = "10.1109/IEDM.2017.8268483",
language = "English",
isbn = "9781538635599",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "32.1.1--32.1.4",
booktitle = "2017 IEEE International Electron Devices Meeting, IEDM 2017",
address = "United States",
note = "63rd IEEE International Electron Devices Meeting, IEDM 2017 ; Conference date: 02-12-2017 Through 06-12-2017",
}