This paper presents a 20 Mfps 32 × 84 pixels CMOS burst-mode imager featuring high frame depth with a passive in-pixel amplifier. Compared to the CCD alternatives, CMOS burst-mode imagers are attractive for their low power consumption and integration of circuitry such as ADCs. Due to storage capacitor size and its noise limitations, CMOS burst-mode imagers usually suffer from a lower frame depth than CCD implementations. In order to capture fast transitions over a longer time span, an in-pixel CDS technique has been adopted to reduce the required memory cells for each frame by half. Moreover, integrated with in-pixel CDS, an in-pixel NMOS-only passive amplifier alleviates the kTC noise requirements of the memory bank allowing the usage of smaller capacitors. Specifically, a dense 108-cell MOS memory bank (10fF/cell) has been implemented inside a 30μm pitch pixel, with an area of 25 × 30μm2 occupied by the memory bank. There is an improvement of about 4x in terms of frame depth per pixel area by applying in-pixel CDS and amplification. With the amplifier{\textquoteright}s gain of 3.3, an FD input-referred RMS noise of 1mV is achieved at 20 Mfps operation. While the amplification is done without burning DC current, including the pixel source follower biasing, the full pixel consumes 10μA at 3.3V supply voltage at full speed. The chip has been fabricated in imec{\textquoteright}s 130nm CMOS CIS technology. {\textcopyright} (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Wu, L, San Segundo Bello, D, Coppejans, P, Craninckx, J, Wambacq, P & Borremans, J 2017, A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier. in TG Etoh, H Shiraga & TG Etoh (eds), Selected Papers from the 31st International Congress on High-Speed Imaging and Photonics. vol. 10328, 1032803, SELECTED PAPERS FROM THE 31ST INTERNATIONAL CONGRESS ON HIGH-SPEED IMAGING AND PHOTONICS, SPIE, 31st International Congress on High-Speed Imaging and Photonics, Osaka, Japan, 7/11/16. https://doi.org/10.1117/12.2271135
Wu, L., San Segundo Bello, D., Coppejans, P., Craninckx, J., Wambacq, P., & Borremans, J. (2017). A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier. In T. G. Etoh, H. Shiraga, & T. G. Etoh (Eds.), Selected Papers from the 31st International Congress on High-Speed Imaging and Photonics (Vol. 10328). Article 1032803 (SELECTED PAPERS FROM THE 31ST INTERNATIONAL CONGRESS ON HIGH-SPEED IMAGING AND PHOTONICS). SPIE. https://doi.org/10.1117/12.2271135
@inproceedings{e0910e9c77ed491b9750f7c5827d4d0d,
title = "A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier",
abstract = "This paper presents a 20 Mfps 32 × 84 pixels CMOS burst-mode imager featuring high frame depth with a passive in-pixel amplifier. Compared to the CCD alternatives, CMOS burst-mode imagers are attractive for their low power consumption and integration of circuitry such as ADCs. Due to storage capacitor size and its noise limitations, CMOS burst-mode imagers usually suffer from a lower frame depth than CCD implementations. In order to capture fast transitions over a longer time span, an in-pixel CDS technique has been adopted to reduce the required memory cells for each frame by half. Moreover, integrated with in-pixel CDS, an in-pixel NMOS-only passive amplifier alleviates the kTC noise requirements of the memory bank allowing the usage of smaller capacitors. Specifically, a dense 108-cell MOS memory bank (10fF/cell) has been implemented inside a 30μm pitch pixel, with an area of 25 × 30μm2 occupied by the memory bank. There is an improvement of about 4x in terms of frame depth per pixel area by applying in-pixel CDS and amplification. With the amplifier{\textquoteright}s gain of 3.3, an FD input-referred RMS noise of 1mV is achieved at 20 Mfps operation. While the amplification is done without burning DC current, including the pixel source follower biasing, the full pixel consumes 10μA at 3.3V supply voltage at full speed. The chip has been fabricated in imec{\textquoteright}s 130nm CMOS CIS technology. {\textcopyright} (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.",
keywords = "Burst mode readout, CMOS, Image sensor, In-pixel amplifier, Mega-frames per second",
author = "Linkun Wu and {San Segundo Bello}, David and Philippe Coppejans and Jan Craninckx and Piet Wambacq and Jonathan Borremans",
year = "2017",
month = feb,
day = "20",
doi = "10.1117/12.2271135",
language = "English",
volume = "10328",
series = "SELECTED PAPERS FROM THE 31ST INTERNATIONAL CONGRESS ON HIGH-SPEED IMAGING AND PHOTONICS",
publisher = "SPIE",
editor = "Etoh, {Takeharu Goji} and Hiroyuki Shiraga and Etoh, {Takeharu Goji}",
booktitle = "Selected Papers from the 31st International Congress on High-Speed Imaging and Photonics",
address = "United States",
note = "31st International Congress on High-Speed Imaging and Photonics, ICHSIP ; Conference date: 07-11-2016 Through 10-11-2016",
url = "http://www.ichsip-31.org/",
}