A pipelined ADC is presented that exploits the low but very constant (over output swing) open-loop gain characteristic of the ring amplifier (ringamp) to achieve high SFDR in low-voltage nanoscale CMOS designs. A dynamic ringamp biasing scheme using CMOS resistors and an active ringamp-based common-mode feedback (CMFB) are also introduced. The implemented prototype achieves 56.3dB SNDR and 69.2dB SFDR at 600Msps, consuming 14.2mW from a 0.9V supply, resulting in a Figure-of-Merit (FoM) of 44.3fJ/conv.-step.
Lagos Benites, JL, Hershberg, B, Martens, E, Wambacq, P & Craninckx, J 2017, A Single-Channel, 600Msps, 12bit, Ringamp-Based Pipelined ADC in 28nm CMOS. in 2017 Symposium on VLSI Circuits, VLSI Circuits 2017., 8008561, Institute of Electrical and Electronics Engineers ( IEEE ), pp. C96-C97, 2017 Symposium on VLSI Circuits, 5/06/17. https://doi.org/10.23919/VLSIC.2017.8008561
Lagos Benites, J. L., Hershberg, B., Martens, E., Wambacq, P., & Craninckx, J. (2017). A Single-Channel, 600Msps, 12bit, Ringamp-Based Pipelined ADC in 28nm CMOS. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (pp. C96-C97). Article 8008561 Institute of Electrical and Electronics Engineers ( IEEE ). https://doi.org/10.23919/VLSIC.2017.8008561
@inproceedings{795e992a2c7149d59f59ba7f128d8a0e,
title = "A Single-Channel, 600Msps, 12bit, Ringamp-Based Pipelined ADC in 28nm CMOS",
abstract = "A pipelined ADC is presented that exploits the low but very constant (over output swing) open-loop gain characteristic of the ring amplifier (ringamp) to achieve high SFDR in low-voltage nanoscale CMOS designs. A dynamic ringamp biasing scheme using CMOS resistors and an active ringamp-based common-mode feedback (CMFB) are also introduced. The implemented prototype achieves 56.3dB SNDR and 69.2dB SFDR at 600Msps, consuming 14.2mW from a 0.9V supply, resulting in a Figure-of-Merit (FoM) of 44.3fJ/conv.-step.",
author = "{Lagos Benites}, {Jorge Luis} and Benjamin Hershberg and Ewout Martens and Piet Wambacq and Jan Craninckx",
year = "2017",
month = aug,
day = "10",
doi = "10.23919/VLSIC.2017.8008561",
language = "English",
pages = "C96--C97",
booktitle = "2017 Symposium on VLSI Circuits, VLSI Circuits 2017",
publisher = "Institute of Electrical and Electronics Engineers ( IEEE )",
note = "2017 Symposium on VLSI Circuits ; Conference date: 05-06-2017 Through 08-06-2017",
}