Kazemi Esfeh, B., Kilchytska, V., Parvais, B., Planes, N., Haond, M., Flandre, D., & Raskin, J. P. (2017). Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements. In Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings (pp. 228-230). (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ULIS.2017.7962569

@inproceedings{e751d23ec080414e81dd28698a98a650,
title = "Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements",
keywords = "3-port S-parameters, FDSOI, cut-off frequencies",
author = "{Kazemi Esfeh}, B. and V. Kilchytska and B. Parvais and N. Planes and M. Haond and D. Flandre and Raskin, {J. P.}",
year = "2017",
month = jun,
day = "29",
doi = "10.1109/ULIS.2017.7962569",
language = "English",
isbn = "9781509053131",
series = "Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "228--230",
booktitle = "Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings",
address = "United States",
note = "oint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 ; Conference date: 26-06-2017 Through 30-06-2017",
}