In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage (Vmin) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%-30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a 6σ yield target and an isoarea of SRAM bitcells, Vmin of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed VT retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is 2.6× lower than LFET bitcells.
Huynh, BT, Sakhare, S, Ryckaert, J, Yakimets, D, Thean, A, Mercha, A, Verkest, D & Wambacq, P 2016, 'A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs', IEEE Transactions on Electron Devices, vol. 63, no. 2, pp. 643-651. https://doi.org/10.1109/TED.2015.2504729
Huynh, B. T., Sakhare, S., Ryckaert, J., Yakimets, D., Thean, A., Mercha, A., Verkest, D., & Wambacq, P. (2016). A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs. IEEE Transactions on Electron Devices, 63(2), 643-651. https://doi.org/10.1109/TED.2015.2504729
@article{960b8002a78042ae8407d638cd6db0a4,
title = "A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs",
abstract = "In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage (Vmin) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%-30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a 6σ yield target and an isoarea of SRAM bitcells, Vmin of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed VT retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is 2.6× lower than LFET bitcells.",
keywords = "VT targeting, 5nm, 6T-SRAM, CMOS scaling, DTCO, LFET, Vmin, RSNM, Nanowire, VFET, WTP",
author = "Huynh, {Bao Trong} and Sushil Sakhare and Julien Ryckaert and Dimitri Yakimets and Aaron Thean and Abdelkarim Mercha and Diederik Verkest and Piet Wambacq",
year = "2016",
month = feb,
day = "1",
doi = "10.1109/TED.2015.2504729",
language = "English",
volume = "63",
pages = "643--651",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",
}