Markulic, N., Raczkowski, K., Wambacq, P., & Craninckx, J. (2016). A Fractional-n subsampling PLL based on a digital-to-time converter. In Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2016 39th International Convention on (pp. 66-71). Article 10.1109/MIPRO.2016.7522112 https://doi.org/10.1109/MIPRO.2016.7522112

@inproceedings{57791d02f0d44ec09cb4e7f606be54a1,
title = "A Fractional-n subsampling PLL based on a digital-to-time converter",
abstract = "The paper presents a subsampling PLL which uses a 10-bit, 0.5 ps unit step Digital-to-Time Converter (DTC) in the phase-error comparison path for the fractional-N lock. The gain and nonlinearity of the DTC can be digitally calibrated in the background while the PLL operates normally. During fractional multiplication of a 40 MHz reference to frequencies around 10 GHz, the measured jitter is in the range from 176 to 198 fs. The worst measured fractional spur is -57 dBc and the in-band phase noise performance of the PLL is -108 dBc/Hz. The presented analog PLL in advanced 28 nm CMOS achieves a figure-of-merit (FOM) of -246.6 dB that compares well to the recent state-of-the-art.",
author = "Nereo Markulic and Kuba Raczkowski and Piet Wambacq and Jan Craninckx",
year = "2016",
month = jul,
day = "28",
doi = "10.1109/MIPRO.2016.7522112",
language = "English",
isbn = "978-1-5090-2543-5",
pages = "66--71",
booktitle = "Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2016 39th International Convention on",
note = "Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2016 39th International Convention on, MIPRO ; Conference date: 30-05-2016 Through 03-06-2016",
}