We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-All-Around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower IOFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (WNW≤25nm, HNW∼22nm), with increased doping enabling ION improvement without IOFF penalty for WNW ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. VT mismatch performance shows higher AVT with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (dNW≥20-30nm), integrated on the same 300mm Si platform as lateral devices. Low IOFF, IG, and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n/n or p/p) to reduce SRAM area per bit by 39%.
Veloso, A, Parvais, B, Matagne, P, Simoen, E, Huynh-Bao, T, Paraschiv, V, Vecchio, E, Devriendt, K, Rosseel, E, Ercken, M, Chan, BT, Delvaux, C, Altamirano-Sanchez, E, Versluijs, JJ, Tao, Z, Suhard, S, Brus, S, Sibaja-Hernandez, A, Waldron, N, Lagrain, P, Richard, O, Bender, H, Chasin, A, Kaczer, B, Ivanov, T, Ramesh, S, De Meyer, K, Ryckaert, J, Collaert, N & Thean, A 2016, Junctionless gate-All-Around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells. in 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016., 7573409, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2016-September, Institute of Electrical and Electronics Engineers Inc., pp. 1-2, 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016, Honolulu, United States, 13/06/16. https://doi.org/10.1109/VLSIT.2016.7573409
Veloso, A., Parvais, B., Matagne, P., Simoen, E., Huynh-Bao, T., Paraschiv, V., Vecchio, E., Devriendt, K., Rosseel, E., Ercken, M., Chan, B. T., Delvaux, C., Altamirano-Sanchez, E., Versluijs, J. J., Tao, Z., Suhard, S., Brus, S., Sibaja-Hernandez, A., Waldron, N., ... Thean, A. (2016). Junctionless gate-All-Around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells. In 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016 (pp. 1-2). Article 7573409 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2016-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2016.7573409
@inproceedings{e54e2a344ec647348e25d2bbab0d547e,
title = "Junctionless gate-All-Around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells",
abstract = "We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-All-Around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower IOFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (WNW≤25nm, HNW∼22nm), with increased doping enabling ION improvement without IOFF penalty for WNW ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. VT mismatch performance shows higher AVT with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (dNW≥20-30nm), integrated on the same 300mm Si platform as lateral devices. Low IOFF, IG, and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n/n or p/p) to reduce SRAM area per bit by 39%.",
author = "A. Veloso and B. Parvais and P. Matagne and E. Simoen and T. Huynh-Bao and V. Paraschiv and E. Vecchio and K. Devriendt and E. Rosseel and M. Ercken and Chan, {B. T.} and C. Delvaux and E. Altamirano-Sanchez and Versluijs, {J. J.} and Z. Tao and S. Suhard and S. Brus and A. Sibaja-Hernandez and N. Waldron and P. Lagrain and O. Richard and H. Bender and A. Chasin and B. Kaczer and T. Ivanov and S. Ramesh and {De Meyer}, K. and J. Ryckaert and N. Collaert and A. Thean",
year = "2016",
month = sep,
day = "21",
doi = "10.1109/VLSIT.2016.7573409",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--2",
booktitle = "2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016",
address = "United States",
note = "36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 ; Conference date: 13-06-2016 Through 16-06-2016",
}