A Discrete-Time (DT) analog baseband for Software-Defined-Radio (SDR) receivers is presented. A zero-IF baseband signal at the input of a programmable gm is converted to current, which is integrated on a 5th order DT IIR filter with a bandwidth ranging from 150 kHz to 80 MHz. The IIR is followed by a DT amplifier which integrates freely selectable samples to implement active FIR filtering while simultaneously offering variable-gain amplification. This integration happens on the DAC capacitance of a 2x interleaved 10b ADC, which finally quantizes the filtered signal at a maximum rate of 300 MS/s. The 28 nm prototype achieves +10 dBm IIP3, 2 nV/VHz IRN and 52 dB gain range while consuming a maximum power of 15 mW.
Malki, B, Verbruggen, B, Martens, E, Wambacq, P & Craninckx, J 2015, A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS. in 41st European Solid-State Circuits Conference - ESSCIRC. IEEE, pp. 80-83, European Solid-State Circuits Conference, Graz, Austria, 14/09/15. https://doi.org/10.1109/JSSC.2016.2561979
Malki, B., Verbruggen, B., Martens, E., Wambacq, P., & Craninckx, J. (2015). A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS. In 41st European Solid-State Circuits Conference - ESSCIRC (pp. 80-83). IEEE. https://doi.org/10.1109/JSSC.2016.2561979
@inproceedings{06a0af6fc1a94987bf308ad38d4fbd02,
title = "A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS",
abstract = "A Discrete-Time (DT) analog baseband for Software-Defined-Radio (SDR) receivers is presented. A zero-IF baseband signal at the input of a programmable gm is converted to current, which is integrated on a 5th order DT IIR filter with a bandwidth ranging from 150 kHz to 80 MHz. The IIR is followed by a DT amplifier which integrates freely selectable samples to implement active FIR filtering while simultaneously offering variable-gain amplification. This integration happens on the DAC capacitance of a 2x interleaved 10b ADC, which finally quantizes the filtered signal at a maximum rate of 300 MS/s. The 28 nm prototype achieves +10 dBm IIP3, 2 nV/VHz IRN and 52 dB gain range while consuming a maximum power of 15 mW.",
author = "Badr Malki and Bob Verbruggen and Ewout Martens and Piet Wambacq and Jan Craninckx",
year = "2015",
doi = "10.1109/JSSC.2016.2561979",
language = "English",
isbn = "978-1-4673-7470-5",
pages = "80--83",
booktitle = "41st European Solid-State Circuits Conference - ESSCIRC",
publisher = "IEEE",
note = "European Solid-State Circuits Conference ; Conference date: 14-09-2015 Through 18-09-2015",
}