Miyaguchi, K., Parvais, B., Ragnarsson, L.-Å., Wambacq, P., Raghavan, P., Mercha, A., Mocuta, A., Verkest, D., & Thean, A. (2015). Modeling FinFET metal gate stack resistance for 14nm node and beyond. In 2015 International Conference on IC Design & Technology (ICICDT) (pp. 1-4). IEEE.

@inproceedings{4498a18fc42f4cf4bf6d419504f1550c,
title = "Modeling FinFET metal gate stack resistance for 14nm node and beyond",
abstract = "A FinFET high-k replacement metal gate stack resistance model is proposed. Introduction of non-negligible contact resistance existing in boundaries between metal layers achieves a good model accuracy which is validated by FEM-based simulation results in 14nm and 10nm technology nodes. Impact of the contact resistance on digital and analog circuit is investigated, resulting in 20% degradation of analog speed by 5 Ω·μm2 contact resistance. The derived gate resistance model is applicable to further downscaled FinFET technology.",
author = "Kenichi Miyaguchi and Bertrand Parvais and Lars-{\AA}ke Ragnarsson and Piet Wambacq and Praveen Raghavan and A. Mercha and Anda Mocuta and Diederik Verkest and Aaron Thean",
year = "2015",
language = "English",
pages = "1--4",
booktitle = "2015 International Conference on IC Design & Technology (ICICDT)",
publisher = "IEEE",
note = "2015 International Conference on IC Design & Technology (ICICDT) ; Conference date: 01-06-2015 Through 03-06-2015",
}