Spagnolo, A., Verbruggen, B., Wambacq, P., & D'amico, S. (2014). A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs, 61(7), 466-470. https://doi.org/10.1109/TCSII.2014.2327340

@article{cfd746038fe74a14889dcf57ab3fa0d5,
title = "A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS",
abstract = "This brief presents an improved timing scheme for a 4× interleaved 6-bit pipelined binary search (PLBS) analog-to-digital converter (ADC). The individual channel consists of a calibrated fully dynamic PLBS architecture with a 1-bit folding front-end. This work enhances the ADC conversion rate up to 3.5 GS/s, for 4.1-mW power consumption. The peak spurious-free dynamic range and signal-to-noise-plus-distortion ratio (SNDR) are 44.1 and 31.2 dB, respectively, measured for low input frequency. With near-Nyquist input frequency, the SNDR drops to 29.5 dB, yielding an energy-per-conversion step of 48 fJ. The prototype has been fabricated in a 40-nm low-power digital CMOS process. The ADC active area is 250 × 120 μm2.",
author = "Annachiara Spagnolo and Bob Verbruggen and Piet Wambacq and Stefano D'amico",
year = "2014",
doi = "10.1109/TCSII.2014.2327340",
language = "English",
volume = "61",
pages = "466--470",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1549-7747",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "7",
}