D'amico, S., Spagnolo, A., Donno, A., Chironi, V., Wambacq, P., & Baschirotto, A. (2014). A 4.1mW 3.5GS/s 6b time interleaved ADC in 40nm CMOS. IEEE Transactions on Microwave Theory and Techniques, 62(8), 1724-1735.

@article{e7c2a9a8579348d981571dc78cb417aa,
title = "A 4.1mW 3.5GS/s 6b time interleaved ADC in 40nm CMOS",
abstract = "A low-power analog baseband section suitable for 60-GHz receivers using orthogonal frequency-division multiplexing (OFDM) with 16 quadrature amplitude modulation (16-QAM) modulation is presented in this paper. Power efficiency is achieved by combining active-RC with source-follower-based topologies in order to synthesize a custom sixth-order transfer function. The complete chain consists of the cascade of a first-order transimpedance amplifier with finely programmable gain, a fourth-order source-follower-based filter, and a coarse gain first-order programmable gain amplifier. The prototype is implemented in 90-nm CMOS. It achieves a 1-GHz cutoff frequency and programmable gain from 0 to 20 dB with 1-dB step control, drawing 9.5 mA (0-9 dB gain range) or 10.8 mA (10-20 dB gain range) from a 1-V supply. An 8.2-dBm third-order input intercept point and a -145-dBm/Hz input-referred noise power density are measured at 0- and 20-dB gain, respectively. The entire circuit occupies an area of 400 × 390 μm2.",
author = "Stefano D'amico and Annachiara Spagnolo and Andrea Donno and Vincenzo Chironi and Piet Wambacq and Andrea Baschirotto",
year = "2014",
language = "English",
volume = "62",
pages = "1724--1735",
journal = "IEEE Transactions on Microwave Theory and Techniques",
issn = "0018-9480",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",
}